This paper presents a proposal for handling sub-words (bytes, 16 and 32 bit-fields) in word-oriented architectures. The proposal is based on using addresses expressed in units of bytes, and on keeping the low-order bits of the address attached to words read from memory. These bits are used by especial instructions to do the extract/insert operations. The solution holds for any unaligned accesses to sub-words even when the architecture supports only aligned accesses to words. Performance implications for machines with or without caches are examined, and extensions to arbitrary bit fields are proposed.